1. Field of the Invention
The present invention relates to a semiconductor memory device, especially to a random access memory which is formed by using MOS FETs.
2. Description of the Prior Art
A memory cell used in a static random access memory which is formed as a semiconductor memory device, for example, a C-MOS (complementary metal oxide semiconductor) field effect transistor construction which is formed with a flip-flop circuit composed of two pairs of C-MOS invertors and two transmission gates, each gate being formed of one MOS field effect transistor. The transmission gate is placed in an off state by a voltage on the word line when information is stored in the memory cell and the transmission gate is placed in an on state when the information is written in or read out from the memory cell. Bit lines, connected to the flip-flop circuit, write in or read out the information via the transmission gate circuit which is kept in the on state. That is, the word lines and the bit lines are extended vertically and horizontally in mesh form, and the memory cells are connected to each cross point of the word lines and the bit lines.
When an MOS integrated circuit with such memory cells is formed by using an SOS (silicon on sapphire) construction, it is recognized that the access time to the memory cell increases when a gate insulating (silicon dioxide) film of the MOS field effect transistor becomes thinner than 500 [A]. In the memory cell which is formed by using the usual MOS field effect transistor having a bulk construction, as in the memory cell using an MOS field effect transistor having an SOS construction, it is recognized that the access time to the memory cell increases when the gate insulating film of the transistor becomes thinner than 300 [A].
This is due to the following reason. In the random access memory, when the bit lines, for example, are formed by using a metal, such as an aluminum material, the word lines are formed by using a polycrystalline semiconductor material such as polycrystalline silicon material. Therefore, the word line has a high specific resistance and one word line is equivalently represented by an RC network which is formed by risistances R being connected in series, and capacitances C corresponding to the gate capacitance of the MOS field effect transistors forming the transmission gate being connected to the word lines in parallel. The value of the capacitances C in the above RC network increases when the thickness of the gate insulating film decreases; therefore, the delay time (which is the time from when the driving terminal is placed in a high level to when each point of the word line is placed in a high level) of the signal which is supplied from a drive terminal of the word line where a driving transistor is connected increases along the word line. When the MOS random access memory becomes large in size or high in integration density, the word line becomes long, and the problem of the delay time in serious. In the memory cell, which is positioned near the drive terminal, the problem of the delay time is not serious; however, in the memory cell, which is distant from the drive terminal, the problem of the delay time is very serious.
The deterioration of the access time in the random access memory is due to the fact that the word lines are formed by the polycrystalline silicon material; therefore, the following countermeasures can be considered, that is, (a) decreasing the value of the resistance in the polycrystalline silicon material, (b) forming the word line by using an aluminum material. However, with respect to the item (a), the value of the resistance in the polycrystalline silicon material has a certain limitation. With respect to the item (b), when the bit lines are formed by a polycrystalline silicon material, the same problem that occurs in the word lines also occurs in the bit lines. When the bit lines and the word lines are both formed by an aluminum material, the multi layer aluminum wiring construction technique should be used; therefore, the manufacturing process becomes difficult.
The access time to the memory cell is determined by the memory cell having the most delayed response time in the word line, so that the access time of the memory cell is increased. Therefore, MOS field effect transistors having a short channel are used for increasing the speed of the function of the MOS field effect transistor. For the MOS field effect transistors to have a short channel, it is required that the gate insulating film of the transistors be formed by a thin film for the purpose of preventing the short channel effect.